The present invention relates to a semiconductor memory device having a redundant circuit, a memory module having a plurality of such semiconductor memory devices, and a test method of a memory module.
Semiconductor memory devices have increasingly been integrated to a higher degree and increased in capacity. For example, dynamic random access memories (hereinafter referred to as DRAMs) having a memory capacity of 1 gigabit have been put into practical use. Redundant circuits for recovering defective memories are used in these mass storage DRAMs. The redundant circuit stores an address of a defective memory with a nonvolatile storage cell and changes the defective memory into a redundant memory to thereby recover the defective memory. The use of the redundant circuit to recover the defective memory can improve a yield and reduce the cost of the semiconductor memory device. A laser fuse, which cuts polysilicon wiring or metal wiring by a laser light, or an electric fuse, which electrically cuts or breaks and short-circuits polysilicon wiring or metal wiring, is used as the nonvolatile storage cell. Currently, electric fuses are used in many cases because a write operation can be performed even in a process after package assembly.
Recently, further miniaturization has been required for semiconductor memory devices. In many cases, semiconductor memory devices are shipped after they have been assembled into memory modules by semiconductor manufacturers. In these cases, since the memory modules are assembled by the semiconductor manufacturers, an evaluation and analysis operation or a test operation of the memory modules is added by the semiconductor manufacturers. Naturally, since defects are also produced in an assembly process of the memory modules, a recovery operation is performed with redundant circuits.
It is assumed that a malfunction occurs in one of mounted DRAMs or a portion of a DRAM. All of the mounted DRAMs or some of the mounted DRAMs are concurrently operated in a memory module. Accordingly, for example, if an abnormal current value is detected, then the DRAMs should be removed from the module substrate and examined to determine which DRAM has a defect. Furthermore, when a defective bit is to be recovered in a state of a memory module by an electric fuse, a replacement operation with a redundant memory is performed for all of the mounted DRAMs or a plurality of the mounted DRAMs. That is, redundant memories of DRAMs other than the defective DRAM are unnecessarily used, so that a defect recovery operation cannot be performed for those DRAMs.
These problems will be described in detail with reference to FIGS. 1 and 2. In a conventional memory module 1, as shown in FIG. 1, a plurality of DRAMs 3 are mounted on a module substrate 2. FIG. 1 shows an example in which eight DRAMs 3 (U0 to U7) are mounted on the module substrate 2. In this example, each DRAM 3 has an 8-bit arrangement, and the memory module 1 has a 64-bit arrangement. Data of 64 bits are concurrently inputted to or outputted from the memory module 1. In order to concurrently operate all of the DRAMs, common wiring is provided so that address and command signal lines are connected to each of DRAMs. Since all of the DRAMs are operated concurrently, the following problems arise during a test operation.
1) Even if an abnormal current of the memory module 1 is detected, it is impossible to determine which DRAM has a defect. This is because all of the DRAMs are operated even in a test operation for performing current measurement, making it impossible to detect which DRAM is defective.
2) In a test operation performed after the assembly into a memory module, a defective memory that has been detected in the memory module is replaced with a redundant memory by an electric fuse or the like. In this case, when a redundant circuit replacement signal is inputted from an external source, DRAMs other than the defective DRAM are also subjected to a replacement operation with a redundant memory for the following reasons. For example, it is assumed that, in a memory module having eight DRAMs of U0 to U7 as shown in FIG. 2, defects are detected in the DRAMs U2 and U4 during a test operation after the memory module has been assembled. It is also assumed that a defective bit address in the DRAM U2 is (X=0123, Y=4567) and that a defective bit address in the DRAM U4 is (X=4321, Y=8765). When the defective bit (X=0123, Y=4567) in U2 is replaced by an electric fuse, normal bits of the same address (X=0123, Y=4567) in the DRAMs (U0, U1, and U3 to U7) other than U2 are also replaced because all of the DRAMs are operated concurrently in the memory module. As a result, the redundant memory has been used in the DRAM U4. Accordingly, the defective bit (X=4321, Y=8765) in U4 cannot be replaced or recovered with the redundant memory.
In order to avoid these problems, there may be a method of selecting a DRAM with use of data signals that are independently assigned to respective DRAMs. However, general memory test devices cannot output data in which all data signals are completely independent, and most of them can merely output certain data signals repeatedly. Accordingly, even if such a function is used, bits of the same address are simultaneously replaced in about four or two out of eight DRAMs. Thus, redundant memories are unnecessarily used in several DRAMs other than a defective DRAM. Therefore, when these DRAMs include a defective bit, they lack redundant memories, so that the defective bits cannot be replaced in those DRAMs.
3) Recently, operating currents of memory modules have been increased by speeding-up of DRAMs and high-density packaging. Memory test devices having a limited power source capability cannot perform a test operation on such high-current memory modules because of voltage drops.
The following patent documents are prior art references relating to such redundant circuits.
Patent Document 1 (Japanese laid-open patent publication No. 2003-338193): A bare chip has an activation/deactivation control pad in addition to an input/output control pad. When the bare chip has a defect, it is brought into a deactivation state.
Patent Document 2 (Japanese laid-open patent publication No. 2003-346496): A semiconductor memory device has a defect information storage table for storing defect information including defective memory addresses and the number of defects in the defective memory addresses, in addition to r row redundant circuits and c column redundant circuits.
However, neither Patent Document 1 nor 2 has any descriptions or technical suggestions relating to the subject matter of the present invention.
As described above, in a conventional memory module, since a plurality of mounted DRAMs are concurrently operated during a test operation, a defective DRAM cannot be specified. Furthermore, redundant circuits in DRAMs other than a defective DRAM are unnecessarily used for the recovery of the defective DRAM.